Single board computers (SBCs) are becoming widely used general purpose data plane processing boards for Advanced Telecom Computing Architecture (ATCA) systems compliant with various protocols such as Peripheral Component Interconnect Industrial Computer Manufacturers Group (PICMG) specifications. Such SBCs are widely used in blade server systems as may be used in various telecommunications applications, data centers, and so forth. Some specifications such as the PICMG, Advanced TCA Base Specification 3.0 enforce a slot power budget limit on the SBCs, e.g., corresponding to 200 watts (W).
For platform architectures, memory becomes a significant component for optimizing power for optimal board performance. However, many power management solutions with respect to memory are very complicated and require great efforts and troubleshooting to design and meet various latency requirements, often with little power savings. In servers, it is difficult to implement memory dynamic power management schemes due to a large number of memory modules requiring individual control of rank level control signals. For telecommunications workloads requiring high reliability from a memory subsystem it becomes a very complex validation effort to enable rank level control. This is particularly the case with regard to techniques directed at fine-grained control of memory power consumption, which often do not save significant power and can cause latency concerns on leaving a low power state.